The invention relates to a semiconductor memory device, and to a method for operating a semiconductor memory device.
In DRAMs, the respective memory cells may, for instance, consist substantially of capacitors. The memory cells/capacitors are adapted to be connected with bit lines that serve to transmit a data value that is to be read out from the memory cell, or a data value that is to be read into the memory cell.
During the reading out from a memory cell, an access transistor that is connected with the capacitor of a memory cell is connected through by the activation of a word line, and the charge state stored in the capacitor is applied to the bit line.
Then, the weak signal emanating from the capacitor is amplified by a read or write/sense amplifier. The read or write/sense amplifier includes complementary signal inputs. The bit lines connected with these signal inputs are referred to as bit line and complementary bit line.
In today's DRAMs, “shared sense amplifiers” may be used as read or write/sense amplifiers so as to save chip space. In so doing, a read or write/sense amplifier is used both during the reading out of a memory cell at the left side and of a memory cell at the right side along respective bit lines that are associated with a read or write/sense amplifier.
Prior to the reading out of the memory cells, the corresponding bit line sections, i.e. the corresponding sections of the non-complementary bit line and of the complementary bit line, are precharged to the same potential by using precharge/equalize circuits that are connected with the bit lines. This potential may, for instance, correspond to half the voltage of a bit line in a logic high state (i.e. VBLH/2). This ensures that—prior to the reading out of data—no differences occur between the potential of the section of the bit line and the section of the corresponding complementary bit line, which could otherwise overlay the small quantity of charge that is transmitted by the capacitor of a memory cell to the bit lines during the reading out. Directly prior to the reading out of the memory cells, the precharge/equalize circuits that are connected with the bit line sections that are associated with the memory cell to be read out are switched off.
Known DRAMs include additionally isolation circuits with isolation transistors which serve to disconnect the read or write/sense amplifier during the reading out of the memory cells from the side/the bit line sections that is/are not connected with the memory cells to be read out.
Each isolation circuit may, for instance, consist of two NMOS-FETs, the source drain paths of which are adapted to interrupt the corresponding bit line sections.
In the known DRAMs, appropriate bias voltages are applied to the gates of the isolation transistors of the isolation circuits beyond the read and write cycles. These bias voltages may, for instance, correspond to a voltage (VINT) generated internally in the DRAM device.
Directly prior to the reading out of a memory cell, that side of the read or write/sense amplifier that is connected with the memory cells that are not to be read out is uncoupled from the corresponding bit line section(s) in that the gates of the corresponding isolation transistors which are positioned on this side of the read or write/sense amplifier are grounded. At the same time, the other side of the read or write/sense amplifier can be coupled with the corresponding bit line section(s) in an improved manner in that the gate voltage that is applied to the gates of the isolation transistors which are positioned at the other side of the read or write/sense amplifier is, for instance, increased from the above-mentioned initial value VINT, to a voltage value VPP.
The actual reading out of the memory cell is initiated shortly thereafter in that corresponding word line signals connect through the access transistors that are connected with the memory capacitors. Then, corresponding activation voltages are applied to the read or write/sense amplifier, whereupon the read or write/sense amplifier amplifies the potential differences that are transmitted by the memory capacitors to the corresponding bit line sections, and outputs a correspondingly amplified differential signal.
The correspondingly amplified differential signal is transmitted by the read or write/sense amplifier to corresponding local data lines, wherein the local data lines are adapted to be coupled to the read or write/sense amplifiers by using corresponding transistors (“bit switches”).
To connect the local data lines with the read or write/sense amplifier, a control signal CSL applied to the gate of the above-mentioned transistors (bit switches) is placed in a logic high state (e.g., the above-mentioned voltage VINT), so that the corresponding transistors (bit switches) are connected through.
The above-mentioned amplified differential signal is transmitted by the local data lines to corresponding global data lines and, for further amplification, to a further sense amplifier (so-called “secondary sense amplifier”).
The driver circuit for the above-mentioned control signal CSL applied to the gate of the above-mentioned transistors (bit switches) may be a simple inverter that enables the switching of the CSL signal between e.g., 0 V and e.g., VINT.
For the above-mentioned reading out of memory cells (“read access”), both local data lines (e.g., called LocalDataLine_t and LocalDataLine_c) that are associated with a corresponding read or write/sense amplifier may first of all be precharged to a voltage level of, for instance, VBLH (wherein VBLH is, for instance, smaller than VINT).
If CSL is activated, a first one of the above-mentioned local data lines (e.g., LocalDataLine_c) may—depending on the state of the read or write/sense amplifier—slowly be discharged by the corresponding bit switch transistor, wherein the resulting differential signal (as mentioned above) is transmitted to the above-mentioned global data lines and to the above-mentioned further amplifier (secondary sense amplifier).
In order to write data in the memory cells (“write access”), for instance, in order to write a “0”, a second one of the above-mentioned local data lines (e.g., LocalDataLine_t) that is associated with the above-mentioned read or write/sense amplifier may, for instance, be set to 0 V while the other one of the above-mentioned local data lines (e.g., LocalDataLine_c) continues to be kept on the above-mentioned precharge voltage level of, for instance, VBLH.
The logic low voltage level of the above-mentioned LocalDataLine_t is applied to a corresponding bit line of the bit line pair which is associated with the corresponding read or write/sense amplifier, which results in that the read or write/sense amplifier switches over or tilts, respectively.
In the case of conventional DRAMs, a constant, unchanged substrate potential is used for the transistors available in the read or write/sense amplifier during the operation of the read or write/sense amplifier or during the above-mentioned write/read cycles, respectively.
For these and other reasons, there is a need for the present invention.